M1025,M1025-1Z-125.0000,M1025-1Z-155.5200,M1025-1Z-156.2500,M1025-1Z-156.8324,M1025-1Z-16

Part No.:
M1025,M1025-1Z-125.0000,M1025-1Z-155.5200,M1025-1Z-156.2500,M1025-1Z-156.8324,M1025-1Z-16
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Description:
VCSO BASED CLOCK PLL WITH AUTOSWITCH
File Size:
341 K
Page:
14 Pages
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Maker:
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
PCB Prototype

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PCB Datasheet:1PCB Datasheet:1
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
MR_SEL3
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Pin-selectable feedback and reference divider ratios
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
28
29
30
31
32
33
34
35
36
M1025
M1026
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
F
EATURES
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
(M1025)
(M1026)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
PLL Ratio
(Pin Selectable)
(M1025)
(M1026)
Output Clock
(MHz)
(Pin Selectable)
19.44 or 38.88
77.76
155.52
622.08
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
M1025/26
NBW
MUX
PLL
Phase
Detector
Loop Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
Auto
Ref Sel
0
R Div
VCSO
1
0
1
M Divider
LOL
Phase
Detector
LOL
FOUT
nFOUT
MR_SEL3:0
4
M/R
Divider
LUT
P Divider
(1, 2, or TriState)
TriState
P_SEL1:0
2
P Divider
LUT
Figure 2: Simplified Block Diagram
M1025/26 Datasheet Rev 1.0
M1025/26 VCSO Based Clock PLL with AutoSwitch
Revised 28Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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