EVAL-ADAU1442EBZ,EVAL-ADAU1446EBZ

Part No.:
EVAL-ADAU1442EBZ,EVAL-ADAU1446EBZ
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Description:
SigmaDSP Digital Audio Processor
File Size:
1008 K
Page:
92 Pages
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PCB Prototype

July 16, 2018:

EVQQ0C

FA10342_OSS-W

FAN5236_10

FAN7171

FAN8200DTF

FP144

FR1112H

FYSH-0335UXC-66-12V-WW8

G5LA1A4-E-CFVDC

G5Q-1A4-DC24

GS816036T-250I

GX434CTC

PCB Datasheet:1PCB Datasheet:1PCB Datasheet:1
SigmaDSP Digital Audio Processor
with Flexible Audio Routing Matrix
ADAU1442/ADAU1445/ADAU1446
FEATURES
Fully programmable audio digital signal processor (DSP) for
enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz
4k parameter RAM, 8k data RAM
Flexible audio routing matrix (FARM)
24-channel digital input and output
Up to 8 stereo asynchronous sample rate converters
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)
Stereo S/PDIF input and output
Supports serial and TDM I/O, up to f
S
= 192 kHz
Multichannel byte-addressable TDM serial port
Pool of 170 ms digital audio delay (at 48 kHz)
Clock oscillator for generating master clock from crystal
PLL for generating core clock from common audio clocks
I
2
C and SPI control interfaces
Standalone operation
Self-boot from serial EEPROM
4-channel, 10-bit auxiliary control ADC
Multipurpose pins for digital controls and outputs
Easy implementation of available third-party algorithms
On-chip regulator for generating 1.8 V from 3.3 V supply
100-lead TQFP and LQFP packages
Temperature range: −40°C to +105°C
APPLICATIONS
Automotive audio processing
Head units
Navigation systems
Rear-seat entertainment systems
DSP amplifiers (sound system amplifiers)
Commercial audio processing
FUNCTIONAL BLOCK DIAGRAM
SPI/I
2
C* SELFBOOT
MP[3:0]/
MP[11:4] ADC[3:0]
XTALI XTALO
ADAU1442/
ADAU1445/
ADAU1446
1.8V
REGULATOR
I
2
C/SPI CONTROL
INTERFACE
AND SELF-BOOT
MP/
AUX ADC
PLL
CLOCK
OSCILLATOR
CLKOUT
SPDIFI
S/PDIF
RECEIVER
PROGRAMMABLE AUDIO
PROCESSOR CORE
S/PDIF
TRANSMITTER
SPDIFO
FLEXIBLE AUDIO ROUTING MATRIX
(FARM)
SDATA_IN[8:0]
(24-CHANNEL
DIGITAL AUDIO
INPUT)
SERIAL
DATA
INPUT PORT
(×9)
SERIAL DATA
OUTPUT PORT
(×9)
SDATA_OUT[8:0]
(24-CHANNEL
DIGITAL AUDIO
OUTPUT)
UP TO 16 CHANNELS OF
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
SERIAL CLOCK
DOMAINS
(×12)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
07696-001
*SPI/I
2
C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.
THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.
Figure 1.
Rev. C
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