NE5520279A,NE5520279A-T1-A

Part No.:
NE5520279A,NE5520279A-T1-A
Download:
Download
Description:
3.2 V, 2 W, L&S BAND MEDIUM POWER SILICON LD-MOSFET
File Size:
352 K
Page:
8 Pages
Logo:
Maker:
CEL [ CALIFORNIA EASTERN LABS ]
PCB Prototype

July 16, 2018:

NE556

NX-09T-F9

NZT7053

OMAPL138BZCE3

OPA1644AIPWR

P0720E

PAM2304

PC312XDP512J1VFVR

PC87591L

PCA9535A

PCEB02

PCIE361

PCB Datasheet:1PCB Datasheet:1
NEC'
S
3.2 V, 2 W, L&S BAND NE5520279A
MEDIUM POWER SILICON LD-MOSFET
FEATURES
• LOW COST PLASTIC SURFACE MOUNT PACKAGE:
5.7
x
5.7
x
1.1 mm MAX
• HIGH OUTPUT POWER:
+32 dBm TYP
5.7 MAX.
0.6±0.15
OUTLINE DIMENSIONS
(Units in mm)
PACKAGE OUTLINE 79A
(Bottom View)
4.2 MAX.
Source
1.5±0.2
Source
0X001
4.4 MAX.
• HIGH POWER ADDED EFFICIENCY:
45% TYP at 1.8 GHz
• SINGLE SUPPLY:
2.8 to 6.0 V
A
0.4±0.15
5.7 MAX.
0.8±0.15
1.0 MAX.
0.8 MAX.
3.6±0.2
DESCRIPTION
NEC's NE5520279A is an N-Channel silicon power laterally
diffused MOSFET specially designed as the power amplifier
for mobile and fixed wireless applications. Die are manu-
factured using NEC's NEWMOS technology (NEC's 0.6
μm
WSi gate lateral MOSFET) and housed in a surface mount
package.
APPLICATIONS
• DIGITAL CELLULAR PHONES:
3.2 V DCS1800 Handsets
• 0.7-2.5 GHz FIXED WIRELESS ACCESS
• W-LAN
• SHORT RANGE WIRELESS
• RETAIL BUSINESS RADIO
• SPECIAL MOBILE RADIO
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C)
PART NUMBER
PACKAGE OUTLINE
Functional
Characteristics
SYMBOLS
P
OUT
G
L
CHARACTERISTICS
Output Power
Linear Gain
Power Added Efficiency
Drain Current
Gate-to-Source Leakage Current
Saturated Drain Current
(Zero Gate Voltage Drain Current)
Gate Threshold Voltage
Transconductance
Drain-to-Source Breakdown Voltage
Thermal Resistance
UNITS
dBm
dB
%
mA
nA
nA
V
S
V
°C/W
15
1.0
40
MIN
30.5
NE5520279A
79A
TYP
32.0
10
45
800
100
100
1.4
1.3
18
8
1.9
V
GS
= 5.0 V
V
DS
= 6.0 V
V
DS
= 3.5 V, I
DS =
1 mA
V
DS
= 3.5 V, I
DS =
700 mA
I
DSS
= 10
μA
Channel-to-Case
MAX
TEST CONDITIONS
f = 1.8 GHz, V
DS
= 3.2 V,
I
DSQ
= 700 mA, P
IN
= 25 dBm, except
P
IN
= 5 dBm for Linear Gain
η
ADD
I
D
I
GSS
I
DSS
V
TH
g
m
BV
DSS
R
TH
Electrical DC
Characteristics
Notes:
1. DC performance is 100% testing. RF performance is testing several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
2. P
in
= 5 dBm
0.9±0.2
California Eastern Laboratories
0.2±0.1
1.2 MAX.
• HIGH LINEAR GAIN:
10 dB TYP @ 1.8 GHz
2
Gate
Drain
Gate
Drain