SN74ACT16373QDLREP,SN74ACT16373Q-EP

Part No.:
SN74ACT16373QDLREP,SN74ACT16373Q-EP
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Download
Description:
16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS
File Size:
309 K
Page:
10 Pages
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Maker:
TI [ TEXAS INSTRUMENTS ]
PCB Prototype

July 16, 2018:

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PCB Datasheet:1PCB Datasheet:1
SN74ACT16373Q-EP
16-BIT D-TYPE TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
SCAS678B – MAY 2002 – REVISED JULY 2002
D
D
D
D
D
D
D
D
D
D
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
–40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree
Member of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Bus Driving True Outputs
Full Parallel Access for Loading
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
DL PACKAGE
(TOP VIEW)
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, highly
accelerated stress test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life.
description
The SN74ACT16373Q-EP is a 16-bit D-type
transparent latch with 3-state outputs, designed
specifically for driving highly capacitive or
relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
This device can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data
(D) inputs if the latch-enable (LE) input is taken high. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
in a bus-organized system, without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1