SN74AUP1G08,SN74AUP1G08DBVR,SN74AUP1G08DBVT,SN74AUP1G08DCKR,SN74AUP1G08DCKT,SN74AUP1G08YE

Part No.:
SN74AUP1G08,SN74AUP1G08DBVR,SN74AUP1G08DBVT,SN74AUP1G08DCKR,SN74AUP1G08DCKT,SN74AUP1G08YE
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Description:
LOW POWER SINGLE 2 INPUT POSITIVE AND GATE
File Size:
271 K
Page:
13 Pages
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Maker:
TI [ TEXAS INSTRUMENTS ]
PCB Prototype

July 16, 2018:

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PCB Datasheet:1PCB Datasheet:1
SN74AUP1G08
LOW POWER SINGLE 2 INPUT POSITIVE AND GATE
SCES502B − NOVEMBER 2003 − REVISED AUGUST 2004
D
Available in the Texas Instruments
D
D
D
D
D
D
NanoStar and NanoFree Packages
Low Static-Power Consumption;
I
CC
= 0.9
µA
Max
Low Dynamic-Power Consumption;
C
pd
= 4.3 pF Typ at 3.3 V
Low Input Capacitance; C
i
= 1.5 pF Typ
Low Noise − Overshoot and Undershoot
<10%
of V
CC
I
off
Supports Partial-Power-Down Mode
Operation
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V
hys
= 250 mV Typ at 3.3 V)
DBV OR DCK PACKAGE
(TOP VIEW)
D
Wide Operating V
CC
Range of 0.8 V to 3.6 V
D
Optimized for 3.3-V Operation
D
3.6-V I/O Tolerant to Support Mixed-Mode
D
D
D
D
Signal Operation
t
pd
= 4.3 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
ESD Protection Exceeds
±5000
V With
Human-Body Model
YEP OR YZP PACKAGE
(BOTTOM VIEW)
D
A
B
GND
1
2
3
5
4
V
CC
Y
GND
B
A
3 4
2
1 5
Y
V
CC
description /ordering information
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire V
CC
range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent
signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
(µA)
100%
80%
60%
40%
20%
0%
AUP
3.3-V
Logic
Dynamic-Power Consumption
(pF)
100%
80%
Voltage − V
60%
40%
20%
0%
AUP
3.3-V
LVC
Logic
Switching Characteristics
at 25 MHz†
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
0
20 25 30
Time − ns
† AUP1G08 data at CL = 15 pF
5
10
15
35
40
45
Input
Output
† Single, dual, and triple gates
Figure 1. AUP − The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This single 2-input positive-AND gate performs the Boolean function Y
+
A
B or Y
+
A
)
B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2004, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1