32 BIT DUAL SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES589B − AUGUST 2004 − REVISED APRIL 2005
Member of the Texas Instruments
Control Inputs V
Referenced to V
Isolation Feature − If Either V
Is at GND, Both Ports Are in the
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
Supports Partial-Power-Down Mode
I/Os Are 4.6-V Tolerant
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 8000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
This 32-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVCH32T245 is optimized to operate with V
set at 1.4 V to 3.6 V. It is operational with V
as low as 1.2 V. The A port is designed to track V
accepts any supply voltage from 1.2 V to 3.6 V. The
B port is designed to track V
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH32T245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
The SN74AVCH32T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 1OE, 2OE, 3OE, and
4OE) are supplied by V
This device is fully specified for partial-power-down applications using I
. The I
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
isolation feature ensures that if either V
input is at GND, then both ports are in the high-impedance
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
−40°C to 85°C
LFBGA − GKE
LFBGA − ZKE (Pb-free)
Tape and reel
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB Prototype
design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265