U1AFS250-FG256,U1AFS250-FG256I,U1AFS250-FGG256,U1AFS250-FGG256I

Part No.:
U1AFS250-FG256,U1AFS250-FG256I,U1AFS250-FGG256,U1AFS250-FGG256I
Download:
Download
Description:
Actel Fusion Mixed-Signal FPGA
File Size:
579 K
Page:
17 Pages
Logo:
Maker:
ACTEL [ Actel Corporation ]
PCB Prototype

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PCB Datasheet:1PCB Datasheet:1
Preliminary v0.4
Actel Fusion Mixed-Signal FPGAs
for the MicroBlade Advanced Mezzanine Card Solution
Features and Benefits
• Targeted to Advanced Mezzanine Card (AdvancedMC™)
Designs
• Designed in Partnership with MicroBlade
• 8051-Based Module Management Controller (MMC)
• Fully Compliant with PICMG AMC.0.R2.0 and IPMI v2.0
Specifications
• AdvancedMC Reference Design and Starter Kit
®
• Crystal Oscillator Support (32 kHz to 20 MHz)
• Programmable Real-Time Counter (RTC)
• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated
PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
Low Power Consumption
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• Sleep and Standby Low Power Modes
High-Performance Reprogrammable Flash
Technology
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Live at Power-Up (LAPU) Single-Chip Solution
350 MHz System Performance
In-System Programming (ISP) and Security
• Secure ISP with 128-Bit AES via JTAG
• FlashLock
®
to Secure FPGA Contents
Advanced Digital I/O
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
– Built-In I/O Registers
– 700 Mbps DDR Operation
• Hot-Swappable I/Os
• Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
• Pin-Compatible Packages across the Fusion Family
Embedded Flash Memory
• User Flash Memory – 2 Mbits to 8 Mbits
– Configurable 8-, 16-, or 32-Bit Datapath
– 10 ns Access in Read-Ahead Mode
• 1 kbit of Additional FlashROM
Integrated A/D Converter (ADC) and Analog I/O
Up to 12-Bit Resolution and up to 600 ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
– P- and N-Channel Power MOSFET Support
– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths
• ADC Accuracy is Better than 1%
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• Programmable Embedded FIFO Control Logic
On-Chip Clocking Support
• Internal 100 MHz RC Oscillator (accurate to 1%)
MicroBlade Fusion Solutions
Fusion Devices
System Gates
Tiles (D-flip-flops)
General Information
Secure (AES) ISP
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
Memory
FlashROM Bits
RAM Blocks (4,608 bits)
RAM kbits
Analog Quads
Analog Input Channels
Analog and I/Os
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
Notes:
1. Refer to the
CoreMP7
datasheet for more information.
2. Refer to the
Cortex-M1
product brief for more information.
U1AFS25
250,000
6,144
Yes
1
18
1
2M
1k
8
36
6
18
6
4
114
24
U1AFS600
600,000
13,824
Yes
2
18
2
4M
1k
24
108
10
30
10
5
172
40
U1AFS1500
1,500,000
38,400
Yes
2
18
4
8M
1k
60
270
10
30
10
5
252
40
October 2008
© 2008 Actel Corporation
I