ADAU1979,ADAU1979WBCPZ,ADAU1979WBCPZ-RL

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ADAU1979,ADAU1979WBCPZ,ADAU1979WBCPZ-RL
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Description:
Quad Analog-to-Digital Converter (ADC)
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PCB Prototype

July 19, 2018:

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ADN4694E

ADP3303ARZ-3.3

ADS1198

ADS54T01

ADSP-21366SKBC-ENG

ADT7302ARTZ-REEL7

ADT7485AARMZ-REEL7

ADUM5400CRWZ2

ADV7850KBCZ-5

AEQ75Y48N-63

AEZ1000RE

PCB Datasheet:1PCB Datasheet:1
Data Sheet
FEATURES
Quad Analog-to-Digital Converter (ADC)
ADAU1979
GENERAL DESCRIPTION
The
ADAU1979
incorporates four high performance, analog-to-
digital converters (ADCs) with 4.5 V rms capable ac-coupled
inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture
with continuous time front end for low EMI. An I
2
C/serial
peripheral interface (SPI) control port is included that allows a
microcontroller to adjust volume and many other parameters.
The
ADAU1979
uses only a single 3.3 V supply. The device
internally generates the required digital DVDD supply. The low
power architecture reduces the power consumption. The on-
chip PLL can derive the master clock from an external clock
input or frame clock (sample rate clock). When fed with the
frame clock, it eliminates the need for a separate high frequency
master clock in the system. The
ADAU1979
is available in a
40-lead LFCSP package.
Note that throughout this data sheet, multifunction pins, such
as SCL/CCLK, are referred to either by the entire pin name or
by a single function of the pin, for example, CCLK, when only
that function is relevant.
Four 4.5 V rms (typical) differential inputs
On-chip phase-locked loop (PLL) for master clock
Low electromagnetic interference (EMI) design
109 dB (typical) analog-to-digital converter (ADC) dynamic
range
Total harmonic distortion + noise (THD + N): −95 dB (typical)
Selectable digital high-pass filter
24-bit stereo ADC with 8 kHz to 192 kHz sample rates
Digital volume control with autoramp function
I
2
C/SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I
2
S, and TDM modes
Master and slave operation modes
40-lead LFCSP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Active noise cancellation systems
FUNCTIONAL BLOCK DIAGRAM
AVDD1
AVDD3
AVDD2
3.3V TO 1.8V
REGULATOR
ADAU1979
AIN1
AIN1
AIN2
AIN2
AIN3
AIN3
AIN4
AIN4
DVDD
AVDDx
ADC
ADC
ADC
ADC
PROGRAMMABLE GAIN
DECIMATOR/HPF
DC CALIBRATION
SERIAL AUDIO PORT
IOVDD
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
AGNDx
AVDDx
BG
REF
AGNDx
PLL
I
2
C/SPI
CONTROL
SCL/CCLK
SDA/COUT
ADDR1/CIN
ADDR0/CLATCH
PD/RST
AGNDx
PLL_FILT
MCLKIN
DGND
VREF
SA_MODE
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
Figure 1.
Rev. 0
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