Preliminary Technical Data
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES,
MPEG2 AAC, MPEG2 2channel, MP3, and functions like
Bass management, Delay, Speaker equalization, Graphic
equalization, and more. Decoder/post-processor algo-
rithm combination support will vary depending upon the
chip version and the system configurations. Please visit
Single-Instruction Multiple-Data (SIMD) computational
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21365/6 is available with a 333 MHz core instruc-
tion rate and unique audio centric peripherals such as the
Digital Audio Interface, S/PDIF transceiver, DTCP (Digital
Content Transmission Protocol) available on the ADSP-
21365 only, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators and more. For
complete ordering information, see
Ordering Guide on
32 X 48-BIT
4 BLOCKS OF ON-CHIP MEMORY
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
JTAG TEST & EMULATION
Figure 1. Functional Block Diagram – Processor Core
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