ADSP-21366,ADSP-21366SKBC-ENG

Part No.:
ADSP-21366,ADSP-21366SKBC-ENG
Download:
Download
Description:
SHARC Processor
File Size:
523 K
Page:
54 Pages
Logo:
Maker:
AD [ ANALOG DEVICES ]
PCB Prototype

July 19, 2018:

ADT7302ARTZ-REEL7

ADT7485AARMZ-REEL7

ADUM5400CRWZ2

ADV7850KBCZ-5

AEQ75Y48N-63

AEZ1000RE

AK8130A

AM50-0006V2

AM55-0003TR

AN-6206

ANT016008LCD1575MA1

AOD417

PCB Datasheet:1PCB Datasheet:1PCB Datasheet:1PCB Datasheet:1
a
SUMMARY
Preliminary Technical Data
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES,
MPEG2 AAC, MPEG2 2channel, MP3, and functions like
Bass management, Delay, Speaker equalization, Graphic
equalization, and more. Decoder/post-processor algo-
rithm combination support will vary depending upon the
chip version and the system configurations. Please visit
www.analog.com/SHARC
SHARC
®
Processor
ADSP-21365/ADSP-21366
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21365/6 is available with a 333 MHz core instruc-
tion rate and unique audio centric peripherals such as the
Digital Audio Interface, S/PDIF transceiver, DTCP (Digital
Content Transmission Protocol) available on the ADSP-
21365 only, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators and more. For
complete ordering information, see
Ordering Guide on
page 51
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
4 BLOCKS OF ON-CHIP MEMORY
BLOCK 0
SRAM
1M BIT
BLOCK 1
SRAM
1M BIT
BLOCK 2
SRAM
0.5M BIT
BLOCK 3
SRAM
0.5M BIT
ROM
2M BIT
ROM
2M BIT
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
32
32
64
DM DATA BUS
64
IOA
IOD
IOA
IOD
IOA
IOD
IOA
IOD
PX REGISTER
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
IOP REGISTERS
(MEMORY MAPPED)
6
JTAG TEST & EMULATION
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
SIGNAL
ROUTING
UNIT
I/O PROCESSOR
AND PERIPHERALS
S
Figure 1. Functional Block Diagram – Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SEE “ADSP-21365/6 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781.329.4700
www.analog.com
Fax:781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.