CY8C20000-12LFXI,CY8C20234_09,CY8C20234-12LKXI,CY8C20234-12LKXIT,CY8C20334,CY8C20334-12LQ

Part No.:
CY8C20000-12LFXI,CY8C20234_09,CY8C20234-12LKXI,CY8C20234-12LKXIT,CY8C20334,CY8C20334-12LQ
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Description:
PSoC Programmable System-0n-Chip
File Size:
1450 K
Page:
34 Pages
Logo:
Maker:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype

July 19, 2018:

CY8C20X96

CYW137OXCT

DAJT3WK3P1-1A0N

DAM-7W2P-NMB-K52

DAMAY26PNM

DBMC37PJ101

DBMMP21H1P-J

DCMA-62P-NMB-K47FO

DCMB-37S-NMC-77

DDMMD43C2PJ

DDZ21

DDZ8V2ASF

PCB Datasheet:1PCB Datasheet:1PCB Datasheet:1PCB Datasheet:1
CY8C20234, CY8C20334
CY8C20434, CY8C20534
PSoC
®
Programmable System-0n-Chip™
Features
Low Power CapSense™ Block
Configurable Capacitive Sensing Elements
Supports Combination of CapSense Buttons, Sliders, Touch-
pads, and Proximity Sensors
Powerful Harvard Architecture Processor
M8C Processor Speeds Running up to 12 MHz
Low Power at High Speed
2.4V to 5.25V Operating Voltage
Industrial Temperature Range: -40°C to +85°C
Flexible On-Chip Memory
8K Flash Program Storage
50,000 Erase/Write Cycles
512 Bytes SRAM Data Storage
Partial Flash Updates
Flexible Protection Modes
Interrupt Controller
In-System Serial Programming (ISSP)
Complete Development Tools
Free Development Tool (PSoC Designer™)
Full Featured, In-Circuit Emulator, and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Trace Memory
Precision, Programmable Clocking
Internal ±5.0% 6/12 MHz Main Oscillator
Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep
Programmable Pin Configurations
Pull Up, High Z, Open Drain, and CMOS Drive Modes on All
GPIO
Up to 28 Analog Inputs on GPIO
Configurable Inputs on All GPIO
Selectable, Regulated Digital I/O on Port 1
• 3.0V, 20 mA Total Port 1 Source Current
• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux
Common Internal Analog Bus
Simultaneous Connection of I/O Combinations
Comparator Noise Immunity
Low Dropout Voltage Regulator for the Analog Array
Additional System Resources
Configurable Communication Speeds
• I
2
C: Selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: Configurable between 46.9 kHz and 3 MHz
2
I C Slave
SPI Master and SPI Slave
Watchdog and Sleep Timers
Internal Voltage Reference
Integrated Supervisory Circuit
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Config LDO
PSoC
CORE
System Bus
Global Analog Interconnect
SRAM
512 Bytes
Interrupt
Controller
SROM
Flash 8K
Sleep and
Watchdog
CPU Core
(M8C)
6/12 MHz Internal Main Oscillator
ANALOG
SYSTEM
CapSense
Block
Analog
Ref.
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Analog
Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-05356 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 16, 2009
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