PC28F512P30BF,PC28F512P30EF,PC28F512P30EFA,PC28F512P30TF

Part No.:
PC28F512P30BF,PC28F512P30EF,PC28F512P30EFA,PC28F512P30TF
Download:
Download
Description:
Micron Parallel NOR Flash Embedded Memory (P30-65nm)
File Size:
1225 K
Page:
92 Pages
Logo:
Maker:
MICRON [ MICRON TECHNOLOGY ]
PCB Prototype

July 19, 2018:

PD0120.702

PE-53682NL

PFP-50N

PMM5303

POE60F-12L

PQ015EN01ZPH

PQ1K213M2ZP

PR2FPXX

PS12064DZS-F

PS2401_1

PT8122C

PTH04T240FAZT

PCB Datasheet:1PCB Datasheet:1
512Mb, 1Gb, 2Gb: P30-65nm
Features
Micron Parallel NOR Flash Embedded
Memory (P30-65nm)
JS28F512P30BFx, JS28F512P30EFx, JS28F512P30TFx,
PC28F512P30BFx, PC28F512P30EFx, PC28F512P30TFx
JS28F00AP30BFx, JS28F00AP30TFx, JS28F00AP30EFx,
PC28F00AP30BFx, PC28F00AP30TFx, PC28F00AP30EFx,
RC28F00AP30BFx, RC28F00AP30TFx, PC28F00BP30EFx
Features
• High performance
• Easy BGA package features
– 100ns initial access for 512Mb, 1Gb Easy BGA
– 105ns initial access for 2Gb Easy BGA
– 25ns 16-word asychronous page read mode
– 52 MHz (Easy BGA) with zero WAIT states and
17ns clock-to-data output synchronous burst
read mode
– 4-, 8-, 16-, and continuous word options for burst
mode
• TSOP package features
– 110ns initial access for 512Mb, 1Gb TSOP
• Both Easy BGA and TSOP package features
– Buffered enhanced factory programming (BEFP)
at 2 MB/s (TYP) using a 512-word buffer
– 1.8V buffered programming at 1.46 MB/s (TYP)
using a 512-word buffer
• Architecture
– MLC: highest density at lowest cost
– Symmetrically blocked architecture (512Mb, 1Gb,
2Gb)
– Asymmetrically blocked architecture (512Mb,
1Gb); four 32KB parameter blocks: top or bottom
configuration
– 128KB main blocks
– Blank check to verify an erased block
• Voltage and power
– V
CC
(core) voltage: 1.7–2.0V
– V
CCQ
(I/O) voltage: 1.7–3.6V
– Standy current: 70µA (TYP) for 512Mb; 75µA
(TYP) for 1Gb
– 52 MHz continuous synchronous read current:
21mA (TYP), 24mA (MAX)
• Security
– One-time programmable register: 64 OTP bits,
programmed with unique information from Mi-
cron; 2112 OTP bits available for customer pro-
gramming
– Absolute write protection: V
PP
= V
SS
– Power-transition erase/program lockout
– Individual zero-latency block locking
– Individual block lock-down
– Password access
• Software
25μs
(TYP) program suspend
25μs
(TYP) erase suspend
– Flash Data Integrator optimized
– Basic command set and extended function Inter-
face (EFI) command set compatible
– Common flash interface
• Density and Packaging
– 56-lead TSOP package (512Mb, 1Gb)
– 64-ball Easy BGA package (512Mb, 1Gb, 2Gb)
– 16-bit wide data bus
• Quality and reliabilty
– JESD47 compliant
– Operating temperature: –40°C to +85°C
– Minimum 100,000 ERASE cycles per block
– 65nm process technology
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2013 Micron Technology, Inc. All rights reserved.