554BDXXXXXXBG,554BDXXXXXXBGR

Part No.:
554BDXXXXXXBG,554BDXXXXXXBGR
Download:
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Description:
SiPHY OC-192/STM-64 TRANSMITTER
File Size:
296 K
Page:
20 Pages
Logo:
Maker:
SILABS [ SILICON LABORATORIES ]
PCB Prototype

July 19, 2018:

5569-05A4S

5569-24A1-210

56800ERM

56F8346

5962-0622901VXC

5962R9583401VXXC

632LP5E

6402

67351-5006

72510

74712-5007

74AC11253

PCB Datasheet:1PCB Datasheet:1
Si5540
P
R E L I M I N A R Y
D
A TA
S
H E E T
SiPHY
OC-192/STM-64 T
RANSMITTER
Features
Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated
16:1 multiplexer and DSPLL
based clock multiplier unit:
Data Rates Supported: OC-192/STM-64,
10GbE, and 10.7 Gbps FEC
Low Power Operation 0.6 W (typ)
Small Footprint: 99-Pin BGA Package
(11 x 11 mm)
OIF SFI-4 Compliant Interface
Output Clock Powerdown
Operates with 155 or 622 MHz
Reference Sources
Optional 3.3 V Supply Pin for
LVTTL Compatible Outputs
Single 1.8 V Supply Operation
Si5364
DSPLL™ Based Clock Multiplier Unit
w/ selectable loop filter bandwidths
Bottom View
Applications
Sonet/SDH/ATM Routers
Add/Drop Multiplexers
Digital Cross Connects
Optical Transceiver Modules
Sonet/SDH Test Equipment
Ordering Information:
See page 17.
Description
The Si5540 is a fully integrated low-power transmitter for high-speed serial
communication systems. It combines high speed clock generation with a 16:1
multiplexer to serialize data for OC-192/STM-64 applications. The Si5540 is based
on Silicon Laboratories’ DSPLL
technology which eliminates the external loop
filter components required by traditional clock multiplier units. In addition,
selectable loop filter bandwidths are provided to ensure superior jitter performance
while relaxing the jitter requirements on external clock distribution subsystems.
Support for data streams up to 10.7 Gbps is also provided for applications that
employ forward error correction (FEC).
The Si5540 represents a new standard in low jitter, low power and small size for
10 Gbps serial transmitters. It operates from a single 1.8 V supply over the
industrial temperature range (–40°C to 85°C).
Functional Block Diagram
R EFSEL
R EFC LK
2
R EFRATE
TXC LK16IN
TXLOL
BW SEL
TXC LKD SBL
TXCL KOUT
TXDOU T
2
16:1
MUX
FIFO
2
R eset
Con trol
D SPLL
TM
CMU
2
2
32
÷
16
TXCL K16OU T
TXCL K16IN
TXDIN [15:0]
FIF ORST
B ias
R EXT
RES ET
F IFOER R
TXSQLC H
TX M SBSEL
Preliminary Rev. 0.31 8/01
Copyright © 2001 by Silicon Laboratories
Si5540-DS031
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.