ST72324J6T

Part No.:
ST72324J6T
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Description:
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
File Size:
1562 K
Page:
156 Pages
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Maker:
STMICROELECTRONICS [ STMICROELECTRONICS ]
PCB Prototype
PCB Datasheet:141PCB Datasheet:141PCB Datasheet:141
ST72324J/K
12.12 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Symbol
f
ADC
V
AREF
V
AIN
I
L
R
AIN
C
AIN
f
AIN
C
ADC
t
STAB
Parameter
ADC clock frequency
Analog reference voltage
2)
3)
Conditions
Min
0.4
0.7*V
DD
V
SSA
Typ
1)
Max
2
5.5
V
AREF
Unit
MHz
V
Conversion voltage range
Input leakage current
for analog input
External input impedance
-40°C≤T
A
≤85°C
range
±250
±1
see
Figure 93
and
Figure
94
3)4)5)
12
0
5)
7.5
4
11
nA
µA
kΩ
pF
Hz
pF
Other T
A
ranges
External capacitor on analog input
Variation freq. of analog input signal
Internal sample and hold capacitor
Stabilization time after ADC enable
f
CPU
=8MHz, SPEED=0
- No of sample capacitor loading cycles f
ADC
=2MHz
- No. of Hold conversion cycles
Conversion time (Sample+Hold)
µs
1/f
ADC
t
ADC
Figure 93. R
AIN
max. vs f
ADC
with C
AIN
=0pF
4)
45
40
35
30
25
20
15
10
5
0
0
10
30
70
Figure 94. Recommended C
AIN
& R
AIN values.5)
1000
Cain 10 nF
2 MHz
Max. R
AIN
(Kohm)
1 MHz
100
Max. R
AIN
(Kohm)
Cain 22 nF
Cain 47 nF
10
1
0.1
0.01
0.1
1
10
C
PARASITIC
(pF)
f
AIN
(KHz)
Figure 95. Typical A/D Converter Application
V
DD
V
T
0.6V
ST72XXX
2kΩ(max)
R
AIN
V
AIN
C
AIN
AINx
10-Bit A/D
Conversion
C
ADC
6pF
V
T
0.6V
I
L
±1µA
Notes:
1. Unless otherwise specified, typical data are based on T
A
=25°C and V
DD
-V
SS
=5V. They are given only as design guide-
lines and are not tested.
2. When V
DDA
and V
SSA
pins are not available on the pinout, the ADC refers to V
DD
and V
SS
.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. C
PARASITIC
represents the capacitance of the PCB Prototyping (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high C
PARASITIC
value will downgrade conversion accuracy. To remedy this, f
ADC
should be reduced.
5. This graph shows that depending on the input signal variation (f
AIN
), C
AIN
can be increased for stabilization and to allow
the use of a larger serial resistor (R
AIN)
.
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