74AC11253

Part No.:
74AC11253
Download:
Download
Description:
DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
File Size:
97 K
Page:
7 Pages
Logo:
Maker:
TI [ TEXAS INSTRUMENTS ]
PCB Prototype

July 19, 2018:

74ACT16863DL

74LVC1G240DCKTG4

75117-1118

760930001

770584-1

801-91-016-10-003

813322BK-02T

84334C

85013-2012

85042-0074

87759-1264

87824-0010

PCB Datasheet:1
54AC11253, 74AC11253
DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCAS041A – MAY 1988 – REVISED APRIL 1993
Permits Multiplexing From N Lines to
One Line
Performs Parallel-to-Serial Conversion
Flow-Through Architecture Optimizes
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
54AC11253 . . . J PACKAGE
74AC11253 . . . D OR N PACKAGE
(TOP VIEW)
t
A
B
1Y
GND
2Y
1G
2G
2C3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1C0
1C1
1C2
1C3
V
CC
2C0
2C1
2C2
54AC11253 . . . FK PACKAGE
(TOP VIEW)
Each of these data selectors/multiplexers
contains inverters and drivers to supply full binary
decoding data selection to the AND-OR gates.
Separate output control inputs are provided for
each of the two four-line sections.
The three-state outputs can interface with and
drive data lines of bus-organized systems. With
all but one of the common outputs disabled (at a
high-impedance state), the low-impedance of the
single enabled output will drive the bus line to a
high or low logic level. Each output has its own
strobe (G). The output is disabled when its strobe
is high.
The 54AC11253 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74AC11253 is characterized for
operation from – 40°C to 85°C.
FUNCTION TABLE
SELECT
INPUTS
B
X
L
L
L
L
H
H
H
H
A
X
L
L
H
H
L
L
H
H
C0
X
L
H
X
X
X
X
X
X
DATA INPUTS
C1
X
X
X
L
H
X
X
X
X
C2
X
X
X
X
X
L
H
X
X
C3
X
X
X
X
X
X
X
L
H
OUTPUT
CONTROL
G
H
L
L
L
L
L
L
L
L
OUTPUT
Y
Z
L
H
L
H
L
H
L
H
1C1
1C0
NC
A
B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1C2
1C3
NC
V CC
2C0
2C1
2C2
NC
2C3
2G
NC – No internal connection
description
logic symbol
1
2
0
1
A
B
1G
1C0
1C1
1C2
1C3
2G
2C0
2C1
2C2
2C3
6
16
15
14
13
7
11
10
9
8
EN
0
1
2
3
3
1Y
1Y
GND
NC
2Y
1G
G
0
3
MUX
5
2Y
Address inputs A and B are common to both sections.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
Copyright
©
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2–1