SN74ACT374,SN74ACT374DBR,SN74ACT374DW,SN74ACT374DWR,SN74ACT374N,SN74ACT374NSR,SN74ACT374P

Part No.:
SN74ACT374,SN74ACT374DBR,SN74ACT374DW,SN74ACT374DWR,SN74ACT374N,SN74ACT374NSR,SN74ACT374P
Download:
Download
Description:
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
File Size:
276 K
Page:
14 Pages
Logo:
Maker:
TI [ TEXAS INSTRUMENTS ]
PCB Prototype

July 19, 2018:

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PCB Datasheet:1
SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F – OCTOBER 1995 – REVISED NOVEMBER 2002
D
D
D
D
4.5-V to 5.5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 10 ns at 5 V
Inputs Are TTL-Voltage Compatible
SN54ACT374 . . . J OR W PACKAGE
SN74ACT374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’ACT374 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in bus-organized systems without need
for interface or pullup components.
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ACT374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
2D
2Q
3Q
3D
4D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PDIP – N
SOIC – DW
–40°C to 85°C
40°C
SOP – NS
SSOP – DB
TSSOP – PW
CDIP – J
–55°C to 125°C
CFP – W
LCCC – FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74ACT374N
SN74ACT374DW
SN74ACT374DWR
SN74ACT374NSR
SN74ACT374DBR
SN74ACT374PWR
SNJ54ACT374J
SNJ54ACT374W
SNJ54ACT374FK
TOP-SIDE
MARKING
SN74ACT374N
ACT374
ACT374
AD374
AD374
SNJ54ACT374J
SNJ54ACT374W
SNJ54ACT374FK
† Package drawings, standard packing quantities, thermal data, symbolization, and Prototype PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4Q
GND
CLK
5Q
5D
1