To appropriately place capacitance with suitable electric capacity near the IC’s power tin can make the output voltage jump faster, the trouble from which is however more than that. The electric capacity has the characteristic of limited frequency response, which makes it impossible for capacitance to produce the harmonic power needed to drive IC output in the full spectrum band. In addition, transient voltage it creates in the process of power confluence will form a voltage drop at the both edges in the path of decoupling, which is the main interference source of the common model EMI. What should we do to deal with these problems?
In terms of IC on the circuit board, power plane around the IC can be seen as a quality high-frequency capacitor, which can used to gather energy the splitting capacitor leaks in the process of clean output intended for providing high-frequency energy. In addition, inductance in the excellent power plane should be small so that the inductance can form small transient signal to reduce common mode EMI.
Of course, the connector between power plane and the pin of IC power should be as short as possible as the rising edge of the digital signal is sharper and sharper, so it is better to directly connect it to the bonding pad where the pin of IC power is, which is another topic.
In order to control the common mode EMI, power plane needs to be helpful to decoupling and has the lowest inductance possible, and therefore needs to be a good match to the power plane with excellent design. Some people may ask, how excellent should it be? The answer to it depends on the layer of power, materials between the layers and working frequency(namely, IC’s rise-time function ). Generally, the gap between layers is 6mil with FR4 in the interlayers and equivalent capacitance in every square inch of power plane is around 75pF. Obviously, the smaller the layer gap is; the larger the capacitance is. There are few components whose rise time ranges from 100ps to 300ps. However, in the near future, there will be more components whose rise time will reach 100ps to 300ps according to IC’s speed of development in the current stage. For circuit whose rise time is 100ps to 300ps, 3-mil layer gap is not suitable for most applications, so layer technique with lay gap less than 1 mil needs to be adopted and materials of high dielectric constant should be employed to replace the dielectric material - FR4. Currently, ceramics and plastics with ceramics can meet the requirements of the rise time ranging from 100ps to 300ps.
In the future, new materials or methods may be adopted. For today’s common circuit whose rise time is 1 to 3ns or whose layer gap is 3 to 6 mil with FR4 as the dielectric material, normally, it is enough to handle the high-end harmonic wave and reduce the transient signal to the lowest possible. That is to say, common mode EMI can be reduced very low. The PCB Manufacturer layer stacking design instance the article provides is based on the assumption that the layer gap is from 3 to 6 mil.
In terms of signal wires, good layering tactics should be to put all the signal wires in one layer or several layers, which should be close to the power layer or ground layer. In terms of power, good layering tactics should make the power layer next to floor layer and the gap between the power layer and floor layer should be as small as possible, which is the “layering” tactics called by us.
What kind of stacking tactics are beneficial to screening and restraining EMI? The following stacking schemes are made based on the assumption that the current flows on one single layer, univoltage or multivoltage are distributed in different parts of the same layer. We will discuss about the muti power layer later.
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